1. Field of the Invention
This invention relates to a microprocessor and, more particularly, to power gating execution units in a microprocessor.
2. Description of the Related Art
Process technology trends in semiconductor manufacturing suggest that power dissipation is a major design challenge in high performance VLSI chips. For all circuit applications it is highly desirable to reduce and limit power dissipation in deep sub-micron semiconductor designs. In high performance server applications, for example, power dissipation leads to expensive packaging and cooling solutions. On the other end of the performance spectrum, the wide spread use of battery operated devices, such a lap top computers, mobile phones and personal digital assistants (PDA's), without significant advances in battery technology, creates an urgent need to address power dissipation in integrated circuits.
Consistent with constant electric field scaling, semiconductor power supply voltages have been substantially reduced with each technology generation. The reduction in power supply voltage is necessary to manage active power dissipation as well as to maintain circuit reliability. With power supply voltage scaling, the device threshold voltage (Vt) must be reduced to maintain or improve performance. Depending on the process technology, this reduction in Vt leads to an exponential increase in sub-threshold leakage current, which, in some cases, may represent the primary source of power dissipation in the chip. Indeed, for current microprocessor designs, power dissipation due to sub-threshold leakage current constitutes 40-50 percent of total chip power. Consequently, a clear need exists to develop novel techniques for controlling and reducing leakage power, especially since leakage power is expected to grow with each new generation of process technology.
Techniques for the control and reduction of leakage current may be divided into two approaches static and dynamic. The static approach to low leakage circuit design is directed to circuit geometries rather than to a functional aspect of the circuit. Such circuit design techniques are intended to reduce leakage current regardless of the mode of chip operation. Dynamic techniques, on the other hand, allow the dynamic control of certain functional blocks of the design during functional operation. In this regard, dynamic techniques involve setting certain functional blocks of the chip into low or no leakage mode when they are in “idle” or “sleep” state. Power gating is one common dynamic leakage control mechanism where circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. When circuit blocks are required for operation once again they are activated to “active model”. These two modes are switched at the appropriate time and in the suitable manner to maximize power performance while minimizing impact to performance.
Modern high performance and power efficient microprocessors use various techniques to clock functional units/macros when in their active state and clock gate logic when in their idle state. These techniques can accommodate pipeline stages based on instruction types and can be data dependent. Thus, active switching power is both reduced and adapted to the workload.
As the scaling of CMOS transistors reaches atomic dimensions, physical effects such as tunneling or sub-threshold leakage currents in CMOS transistors contribute substantially to power dissipation and loss. This loss of power can be reduced substantially by powering off the idle logic macros, i.e., power is gated off to switch off leakage currents between Vdd (supply voltage) and Gnd (ground) level.
Current implementations of power gating use simple state machines controlled by various events such as (branch) miss-predictions or (cache) data misses upon loads or idle counters, which are incremented as long as an instruction is not issued to an execution unit. If the counter reaches a threshold value, the execution unit will be power gated. If instructions are issued to the execution unit, the unit will be re-powered—mostly going through a re-powering sequence- and will then change back to its operational mode once the power is stable and the unit is initialized.
While the process noted above works well for workloads which have phases of high unit usage and phases of long idle periods, power gating of the execution unit will occur during the idle phases which will substantially reduce leakage currents. However, with workloads which periodically show short and regular idle phases of just a few cycles to the execution unit, the idle threshold may not be reached. In addition, when running a mixture of application with different resource requirements simultaneously, multi-threading may cause a periodical issue sequence to various execution units which show short idle phases which are shorter than the threshold value. As a consequence, power gating is never applied and, therefore, energy is not saved because the functional unit stays powered, even during all idle cycles.